Compilation translates a program into operations that a target can execute. For quantum workloads, that translation can change gate decomposition, logical-to-physical placement, routing, operation order, and classical-bit mappings. Understanding those changes is essential because the physical error exposure depends on the compiled implementation.
Portability begins by identifying what must remain equivalent. Two circuits can represent the same ideal unitary while experiencing different noise. Two complete programs can produce equivalent output distributions while using different intermediate measurements. A compiler's correctness claim and a workload's measured quality claim are related, but they are not interchangeable.
Specify the target and the preserved behavior
A target description identifies supported instructions and the resources on which they operate. Depending on the provider, it may also describe durations, connectivity, and other properties. The compiler uses that information to choose a realizable implementation. Preserve the target description or its supplied identifier alongside compiler settings and output artifacts.
For a unitary-only subroutine, equivalence up to global phase may be sufficient. For a program with measurements and classical conditions, correctness must account for outcome distributions and classical control semantics as well. Comparing only a unitary matrix cannot verify a program that resets qubits or branches on measurement results.
The observable mapping is part of the contract. After placement and routing, a result associated with physical qubit P2 might represent logical qubit L0. A correct compiled circuit paired with an incorrect result mapping still produces an incorrect analysis.
The lab's compilation is intentionally simple
The Bell implementation uses Aer, a density-matrix simulator, and transpiles at optimization level zero with a recorded transpiler seed. It also records the simulator seed and limits parallel simulator threads. These choices support a controlled teaching environment; they do not prove that all compiler choices are irrelevant or that seeds alone define an executable artifact.
The complete runnable circuit source is introduced with the shared experiment in chapter 4.
The simulator's ability to execute the model does not establish hardware portability. The inserted noise instruction describes a simulated channel. It must not be submitted as though it were an ordinary physical gate available on an arbitrary device. A hardware experiment requires a target-compatible preparation and measurement program, with noise assessed through separate evidence.
Worked example: preserve a remapped observable
Suppose a compiler maps logical qubit L0 to P2 and logical qubit L1 to P0. The intended measurement is Z on L0, and the circuit stores P2's result in classical bit c1. Qiskit's displayed two-bit strings place c1 on the left. The estimator must therefore read the left bit in this specific mapping.
For ten shots with six left-bit zeros and four left-bit ones, the estimate is (6 − 4)/10 = 0.2. Reading the right bit instead might produce a completely different answer while leaving the job status, circuit execution, and histogram format looking normal.
The Bell parity score can conceal this mistake because swapping its two bits does not change parity. Include an asymmetric test case when validating mapping logic. Tests should exercise the property that might break, rather than relying exclusively on the most symmetric demonstration circuit.
Compare transformations in stages
First check structural validity: supported operations, operand arity, resource constraints, and classical dependencies. Then check ideal behavior using a method appropriate to the program's size and semantics. Small circuits can be compared with exact simulation; larger ones require more selective verification methods and explicit limits.
Finally evaluate the relevant workload under its execution conditions. Fewer gates, lower abstract depth, or a shorter schedule can be useful indicators, but none alone establishes a lower scientific error. Compare output quality, uncertainty, and resource use with compatible experimental contexts.
When a compiler release changes, retain both the old and new artifacts. A semantic version label describes a release policy, not a numerical reproducibility guarantee. A seemingly minor bug fix can legitimately alter placement or results and require renewed workload validation.
Exercise: decide what can be claimed
A new compiler reduces a circuit from 80 to 60 two-qubit gates. Ideal simulator outputs agree on the tested inputs. Can the team claim a 25 percent reduction in hardware error and deploy without further evaluation?
Answer. It can claim a 25 percent reduction in that counted gate resource and agreement on the tested ideal cases. The error reduction does not follow: the new gates may use different couplings, timing, or concurrency, and tested inputs may not establish general semantic equivalence. Evaluate the compiled workload with its target mapping and relevant hardware evidence before making a broader claim.
The hardware chapter explains the constraints compilation must respect. Timing and dynamic circuits extends the discussion to programs whose next action depends on a measurement result.