A dynamic quantum program can use an intermediate measurement result to influence subsequent operations. That capability connects quantum measurement to classical processing inside the execution. It creates a different timing problem from a host application that submits a circuit, waits for its complete result, and then chooses another circuit.
The distinction matters because the quantum information involved in a feedback decision may need to survive while that decision is made. A cloud request-response time, a simulator's CPU time, and a device's internal feedback latency describe different paths. None should be substituted for another without a concrete architecture and measurement.
Follow the actual dependency
A feedback path can include measurement acquisition, discrimination into classical information, transport, decision computation, and dispatch of a conditioned operation. Some stages can overlap with other work; others lie on a dependency path that cannot be bypassed. Scheduled duration must reflect those dependencies and the resources they occupy.
Mid-circuit measurement does not imply arbitrary low-latency classical computation. A target might support only selected conditions or restricted control structures. Reset can have its own implementation and timing constraints. Validate the exact instructions needed by the program, using the target's documented interface.
The local Bell workload does not implement a hardware feedback loop. It samples one completed basis circuit at a time, then performs host-side analysis between checkpoints. Calling that analysis “feedback” in a broad workflow sense does not make it a real-time device controller.
Latency, throughput, and deadlines
Latency measures the elapsed time for a particular item or decision. Throughput measures how many items a system processes per unit time. A highly batched decoder can have excellent average throughput while individual decisions wait for a batch or experience long tails.
The QEC fixture times the host call to decode_batch. It excludes detector sampling and graph construction. Dividing that elapsed time by trial count gives an amortized host decoding cost per complete simulated memory experiment. It does not measure the latency of one hardware syndrome round or establish a feedback deadline guarantee.
A deadline claim needs a defined start event, end event, allowed miss probability, workload distribution, and measurement environment. Include transport and queueing on the relevant path. Average computation time alone is insufficient when delayed decisions can affect a subsequent operation.
Worked example: a synthetic feedback path
Suppose an illustrative controller allows 0.80 microseconds from measurement start to a usable conditioned-operation command. Assume sequential contributions of 0.45 microseconds for readout, 0.08 for transport, 0.20 for decision computation, and 0.05 for dispatch.
The total is 0.78 microseconds, leaving 0.02 microseconds of nominal margin. If decision computation occasionally takes 0.28 microseconds, the same path takes 0.86 microseconds and misses the deadline. This arithmetic is a constructed example, not a measurement of the project or a forecast for a device.
Increasing batch throughput would not necessarily remove that miss. The operator needs evidence about the distribution of end-to-end path times and the consequences of missing the deadline. Possible responses include a different schedule, a bounded fallback, a changed code or protocol, or withholding admission when the requirement cannot be met.
Some corrections can be tracked classically
A Pauli correction often need not be physically applied immediately. A controller can track a Pauli frame and reinterpret later measurements or adapt later operations. This can remove some urgent physical correction operations from the path, but it does not eliminate every timing dependency.
The frame must remain synchronized with logical operations and measurement records. Clifford gates transform Pauli corrections in a tractable way; non-Clifford operations can require additional adaptation. A controller that is merely fast, but propagates the wrong frame, produces incorrect logical interpretations.
The decoder chapter follows an explicit frame trace. Its perfect-check repetition example is useful for understanding information flow, while the surface-code memory fixture adds a separate noisy-circuit experiment.
Exercise: evaluate a benchmark claim
A decoder processes 10,000 stored memory experiments in one batch. A report divides total time by 10,000 and labels the result “hardware feedback latency.” What should the label and accompanying evidence say instead?
Answer. Label it amortized host batch decoding time per simulated memory experiment. State what was timed, the engine and host, the experiment dimensions, and excluded work. Hardware feedback latency requires measurements on the actual end-to-end control path, including relevant transport, queueing, and timing tails. The stored batch benchmark cannot supply those quantities by renaming its denominator.
Use the lab's QEC section to compare logical outcomes with decoder timing while keeping those two kinds of evidence separate.