The earlier chapters treated the QPU as an operational target. This chapter opens the box again and asks a different question: which kind of quantum system are we operating, and what does that choice force us to optimize?
There is no generic quantum computer in the operational sense. A superconducting processor, trapped-ion QCCD machine, neutral-atom analog simulator, photonic machine, annealer, and topological-qubit prototype expose different constraints. They may all be called quantum computers, but they do not fail, schedule, compile, cool, benchmark, or scale in the same way.
The architecture decision is therefore not merely a research preference. It determines the control plane, software stack, data model, facilities plan, supply chain, staffing model, and commercialization path.
19.1 The architecture decision surface
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flowchart TB
Goal[Target workload and product goal] --> Model{Computation model}
Model --> Gate[Gate model]
Model --> Analog[Analog simulation]
Model --> Anneal[Annealing / Ising]
Gate --> Modality{Qubit modality}
Analog --> Modality
Anneal --> Modality
Modality --> Constraints[Physical constraints]
Constraints --> Stack[Control, compiler, scheduler, data stack]
Stack --> Economics[Cost and scaling economics]
Economics --> Roadmap[Roadmap and operating model]A modality decision should begin with the workload and end with the operating model. Reversing that order is a common failure mode: teams pick impressive hardware first and then search for a use case that tolerates its constraints.
19.2 Superconducting processors
Superconducting systems are engineered microwave systems operating at millikelvin temperatures. They are attractive because they can use lithographic fabrication techniques, fast gates, and dense integration paths. They also impose severe requirements on cryogenics, microwave control, cabling, crosstalk management, packaging, and calibration cadence. IBM describes Quantum System Two as combining scalable cryogenic infrastructure, runtime servers, and modular qubit control electronics, which is the right operating lens: the machine is not just a chip; it is a cryogenic-control-compute system [R39].
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flowchart LR
Runtime[Runtime servers] --> Control[Microwave control electronics]
Control --> Lines[Cryogenic wiring and attenuation]
Lines --> Chip[Superconducting QPU]
Chip --> Readout[Readout resonators and amplifiers]
Readout --> Acquire[Acquisition chain]
Acquire --> RuntimeOperational implications:
| Dimension | Superconducting implication |
|---|---|
| gates | fast, but calibration-sensitive |
| topology | usually local connectivity, making routing expensive |
| cooling | dilution refrigerator and cryogenic wiring dominate facilities design |
| drift | frequent recalibration and calibration-aware compilation are central |
| scaling | packaging, control lines, cryogenic heat load, and crosstalk are first-order constraints |
The platform team should treat superconducting machines as high-throughput, high-drift systems. Utilization is useful only when quality is high enough. A busy superconducting QPU in poor calibration is a noise generator.
19.3 Trapped-ion QCCD systems
Trapped-ion systems use ions confined by electromagnetic fields, manipulated with lasers or microwave fields, and often moved through trap regions. Quantinuum’s H2 documentation describes operational details such as gate zones, ion transport, cooling-related constraints, and rebasing into native gates [R18, R40].
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flowchart TB
Queue[Task queue] --> Rebase[Rebase to native ion gates]
Rebase --> Route[Ion transport and zone planning]
Route --> Cool[Cooling / motional-state management]
Cool --> Gate[Laser-mediated gates]
Gate --> Measure[Measurement]
Measure --> Validate[System validation]Operational implications:
| Dimension | Trapped-ion implication |
|---|---|
| connectivity | often high or all-to-all logical connectivity, reducing SWAP pressure |
| gates | slower than superconducting gates, but often high fidelity |
| scheduling | transport and gate-zone contention matter |
| control | laser stability, ion ordering, cooling, and transport become platform concerns |
| scaling | modular trap design, parallel gate zones, and photonic links become relevant |
A trapped-ion scheduler is not just a queue. It is a planner for motion, gate zones, cooling windows, and user-visible circuit restrictions.
19.4 Neutral atoms and analog Hamiltonian simulation
Neutral-atom systems can arrange atoms into programmable geometries and use Rydberg interactions to implement analog Hamiltonian simulation. Amazon Braket’s QuEra Aquila documentation exposes this through an analog Hamiltonian simulation program model rather than an ordinary gate-circuit abstraction [R41].
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flowchart LR
Geometry[Atom arrangement] --> Hamiltonian[Program Hamiltonian]
Hamiltonian --> Schedule[Time-dependent controls]
Schedule --> Evolve[Analog evolution]
Evolve --> Measure[Measurement samples]
Measure --> Infer[Classical inference]Operational implications:
| Dimension | Neutral-atom implication |
|---|---|
| programming | may be analog rather than gate-based |
| layout | atom placement is part of the program |
| validation | simulation may be classically hard at useful sizes |
| data | samples must be interpreted as evidence from an analog process |
| optimization | pulse schedules and geometry can be as important as circuit depth |
Neutral-atom systems widen the book’s core thesis: a quantum workload is not always a circuit. The platform must represent the physical program directly enough that provenance remains meaningful.
19.5 Quantum annealing and Ising machines
Annealing systems target optimization and sampling problems that can be encoded into Ising, QUBO, or related forms. D-Wave’s Ocean SDK is built around this model and gives users tooling for quantum computers and hybrid solvers [R42].
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flowchart TB
Problem[Optimization problem] --> Encode[QUBO / Ising encoding]
Encode --> Embed[Minor embedding / topology mapping]
Embed --> Anneal[Annealing schedule]
Anneal --> Samples[Sample set]
Samples --> Decode[Decode candidate solutions]
Decode --> Hybrid[Hybrid refinement]Operational implications:
| Dimension | Annealing implication |
|---|---|
| workload | optimization and sampling, not universal circuit execution |
| compiler | embedding and penalty-weight selection dominate |
| metrics | best sample, distribution quality, feasibility rate, and energy gap matter |
| hybrid loop | classical repair and refinement are usually part of the product |
| governance | avoid presenting annealing results as universal gate-model results |
An annealer should be operated as a probabilistic optimizer. The result is a candidate set with evidence, not a proof of optimality unless independently certified.
19.6 Photonic and topological paths
Photonic quantum computing and topological-qubit approaches introduce different operating assumptions. Photonic systems emphasize optical components, sources, detectors, switching, loss, and possibly measurement-based computation. Microsoft’s topological-qubit work is framed around Majorana-based devices and a path toward more protected qubits, but practical platform design should still require empirical evidence, workload benchmarks, and resource estimates before treating any roadmap as operational capacity [R43].
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flowchart LR
Architecture[Emerging architecture] --> Promise[Theoretical scaling promise]
Promise --> Evidence{Operational evidence?}
Evidence -- no --> Research[Research track]
Evidence -- partial --> Pilot[Pilot track]
Evidence -- yes --> Platform[Platform track]
Pilot --> Bench[Benchmark and resource estimate]
Bench --> EvidenceThe platform rule is simple: roadmaps are inputs to planning, not substitutes for measured reliability.
19.7 Modality comparison for operators
| Modality | Strong operating fit | Dominant operational risk |
|---|---|---|
| superconducting gate model | fast experimental iteration and circuit workloads | calibration drift, crosstalk, cryogenic scaling |
| trapped ion gate model | high-connectivity circuits and precise operations | slower cycles, transport/control complexity |
| neutral atom analog | Hamiltonian simulation and geometry-rich problems | analog validation and problem-specific programmability |
| annealing | QUBO/Ising optimization and sampling | embedding overhead and interpretation risk |
| photonic | long-term networking and room-temperature optical paths | loss, source quality, detector integration |
| topological | potential reduction in correction overhead | maturity and evidence gap |
View diagram source
quadrantChart
title Modality operating posture
x-axis Lower platform maturity --> Higher platform maturity
y-axis Narrower workload fit --> Broader workload fit
quadrant-1 Scale selectively
quadrant-2 Productize carefully
quadrant-3 Research track
quadrant-4 Specialized service
Superconducting: [0.75, 0.70]
Trapped ion: [0.70, 0.65]
Neutral atom analog: [0.55, 0.45]
Annealing: [0.70, 0.35]
Photonic: [0.35, 0.50]
Topological: [0.25, 0.55]The placement in this diagram is not a universal ranking. It is an operating heuristic. Update it as the evidence changes.
19.8 Architecture selection checklist
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flowchart TB
Start[Architecture candidate] --> Workload[Map to workload class]
Workload --> Capability[Check native capability]
Capability --> Evidence[Review benchmark evidence]
Evidence --> Integration[Assess software and control integration]
Integration --> Facilities[Assess facilities and supply chain]
Facilities --> Cost[Estimate operating cost]
Cost --> Roadmap[Compare roadmap risk]
Roadmap --> Decision{Select?}
Decision -- yes --> Pilot[Run governed pilot]
Decision -- no --> Reject[Reject or defer]Selection questions:
| Question | Required evidence |
|---|---|
| What workload class does this serve? | problem portfolio, baselines, success criteria |
| What abstraction does it expose? | circuit, pulse, analog Hamiltonian, annealing, or service API |
| What must the scheduler know? | topology, calibration, transport, queue, reservations, quality windows |
| What must the compiler know? | native gates, geometry, timing, error model, constraints |
| What breaks most often? | drift, loss, heating, transport failure, embedding failure, detector error |
| What is the upgrade path? | processor replacement, modular expansion, new control electronics, software compatibility |
19.9 Chapter rule
Do not ask, “Which quantum architecture is best?”
Ask:
Which architecture produces trustworthy evidence for our workload, under our operating constraints, with a credible path to improve?
That question is harder. It is also the only one that matters.
References used in this chapter: [R18], [R39], [R40], [R41], [R42], [R43].